1. Field of the Invention
The present invention is related to a multi-channel display driver circuit incorporating modified digital-to-analog (D/A) converters, and more particularly to a modified pulse width modulated D/A converter circuit to convert input digital signals to analog output for data imaging on the display apparatus, capable of overcoming harmonic distortion and electromagnetic interference, that occur in a display driver circuit using conventional pulse width modulation digital-to-analog converters.
2. Description of Prior Art
The so-called digital display actually draws on the various technologies from electro-optics, electronics, biochemistry, and semiconductor domains. A multi-channel display driver is an important component in the new generation of display apparatuses used to control simultaneous output of video data.
In recent years, different multi-channel display driver circuits have been devised by many manufacturers of digital displays to meet requirements for high speed display and to downsize the circuit components.
For conventional multi-channel display driver circuits, in an effort to downsize the circuit components, manufacturers often use pulse width modulated (PWM) digital-to-analog (D/A) converters in the display driver circuit. The architecture of a conventional PWM D/A converter circuit is shown in FIG. 1, comprising a sequential counter (41) and a plurality of parallel digital comparators (40).
The sequential counter (41) may be either an up counter or a down counter, which outputs a sequence signal represented by a given number of bits (n bits) which are the same as the number of bits of a digital data signal received by the D/A converter.
The outputs of the digital comparators (40) are respectively connected to a corresponding data channel of a display apparatus (42) in parallel, and each digital comparator (40) has a digital data input and a reference input, and wherein the reference input is connected to the sequential counter (41) to obtain a sequence signal as a reference signal of the digital comparator (40).
The reference inputs of all digital comparators (40) in the PWM D/A converter circuit are connected to the sequential counter (41) with the same sequence of bits (0-bit.about.n-bit) as shown in FIG. 2, so that all digital comparators (40) use the same reference signals. These reference signals are to be compared with the input digital data signals. If the value of input digital data signal is greater than or equal to that of the reference signal, then the digital comparator (40) will output a high voltage pulse, and if the value of input data digital signal is smaller than that of the reference signal, the digital comparator (40) will output a low voltage pulse.
In FIGS. 3A and 3B, two different waveforms of the output signals are generated from the digital comparator using two different digital data signals in a given time period. If the sequential counter (41) overflows, the sequential counter (41) will be reset to start all over again, and the output of a digital comparator (40) normally terminates at the end of a complete output cycle period. For example using a 10-bit sequential counter, when the sequential counter (41) output sequence signal's value reaches 1024, the sequential counter (41) is reset to start the next output cycle period. The bit-length of each output cycle period is dependent on the number of bits contained in the output of the sequential counter (41) and the clock rate driving the sequential counter (41).
The above PWM D/A converter circuit is mainly consisted of one sequential counter (41) and the plurality of digital comparators (40). Therefore, a multi-channel display driver using this type of D/A converter can be built with a small-size circuit and low costs, but these D/A converters have the following disadvantages.
First, if the output signal of pulse width modulation is sustained for a given time period short of a complete output cycle, the sampled analog signal waveform will tend to concentrate towards either high voltage or low voltage side, thus causing the overshoot distortion of the DC level. Second, flickering will appear on the display apparatus when low order harmonics of pulse width modulated signals are produced.
The flickering phenomenon will further worsen if the number of bits in a digital data signal is extended. This is because the output cycle period of a pulse width modulated signal also has to be extended to cover the extra bits, and the effect of a longer duty cycle will multiply during line scanning, leading to even more serious harmonic distortion and flickering.
For example, if the input digital signal and the counter both are 10 bits, the output signal shall be stored with a normal cycle period of 1024 (210=1024) clocks. If the cycle period of output signal is extended, provided that the clock rate is constant, then the frame rate has to be reduced in inverse proportion. Once the frame rate or screen refresh rate drops to a level that human eyes are able to detect, flickering will appear on the display apparatus. Therefore, the conventional PWM D/A converter circuit is susceptible to low frequency harmonics, and as a result the imaging quality will be degraded. This harmonic distortion phenomenon happens since the sequential counter outputs sequence signals. Therefore, the PWM D/A converter couldn't provide a quality image output although its size is small.
Another D/A converter circuit that uses sigma-delta modulation technique can produce good images. This sigma-delta D/A converter circuit, as shown in FIG. 4, is formed by a plurality of parallel sigma-delta converters (50), wherein each sigma-delta converter (DAC) (50), as shown in FIG. 12, is mainly consisted of an adder (51), a loop filter (52) and a quantizer (53); wherein one input of the adder (51) is used for receiving digital signal input (Digital In), and another input is used to receive the output fed from the quantizer (53), thus forming a feedback loop (54).
The adder (51) in the sigma-delta converter (50) uses the signal fed back by the quantizer (53) to subtract from the digital signal to produce an error signal (Es), and then the error signal (Es) is sampled and again input through the feedback loop (54), where the error signal (Es) is synthesized with subsequent input and then forwarded to the quantizer (53) again through the loop filter (52). As the value of the error signal (Es) represents the difference between the quantized signal and the digital signal, the returned error value through the sigma-delta loop (54) can correct the previous quantizing error to make the output from the quantizer (53) of sigma-delta converter (50) free from first harmonics.
In FIGS. 6A and 6B, from the time-domain signal waveform of two different outputs from the sigma-delta converter, high (512/1024) and low (299/1024) DC levels are dispersed across a given time period. It can be clearly seen that the average DC magnitude of the output in FIG. 6A is greater than that of FIG. 6B (512>299), as the time-domain signal waveform of FIG. 6A is more concentrated than that of FIG. 6B. When these two signals are output to the display apparatus, the image produced by the output of FIG. 6A will be brighter than that of FIG. 6B. From the output time-domain signal waveforms of the sigma-delta converter, it can also be observed that the sampled analog signal waveform from the output of the sigma-delta converter does not have to rely on a complete output cycle period to produce precise DC levels, and yet the summation of sampled high and low levels can closely approximate the target output value. Therefore, overshoot distortion of the DC level will never occur using the sigma-delta modulation technique.
In FIGS. 7A and 7B, from the comparative frequency spectrum of the output from the sigma-delta converter and the PWM D/A converter, it is apparent that the operation of the sigma-delta converter circuit can completely remove the first harmonics due to the reasons already explained in the above paragraph.
Though the above sigma-delta D/A converter circuit produces better results than the PWM D/A converter circuit, the construction of each sigma-delta converter is more complicated. Besides, if the sigma-delta D/A converter circuit is to be applied in a multi-channel data driver, a matching number of sigma-delta converters for multiple data channels will be required. Therefore, the sigma-delta D/A converter circuit will take up more circuit space than the equivalent PWM D/A converter circuit.
The current situation is that D/A converters in multi-channel display driver circuits cannot be downsized and still have good performance, no matter which signal modulation technique is used.